The present invention relates in general to integrated circuits and in particular to clock generation circuits and methods with minimal glitch generation and systems using the same.
Integrated circuit devices are often provided with the capability of operating in response to external master clocks of different frequencies to allow compatibility with a range of system applications. Generally, the given device receives an external master clock of a selected frequency, which is then internally divided down by various ratios to generate a set of internal clocks of different frequencies. One or more of these internal clocks is selected, by a multiplexer or similar circuit, as required for the operation of the corresponding internal circuit blocks.
Audio devices, such as the digital to analog converters (DACs) utilized in digital audio playback systems, typically receive three clocks along with the incoming audio data stream. In particular, the external master clock (MCLK) signal controls the overall timing of the processing operations, the serial or bit clock (SCLK) signal clocks in the individual bits of serial audio data, and the left-right clock (LRCK) signal differentiates between left and right stereo data samples in the incoming data stream. In order to provide compatibility with different external systems, an internal MCLK signal is generated from the external MCLK signal, subject to a number of constraints. Specifically, the internal MCLK signal must have a frequency of at least twice the SCLK signal frequency. At the same time, the frequency of the internal MCLK signal must have a certain oversampling ratio with respect to the frequency of the LRCK signal, often 256xc3x97, 128xc3x97or 64xc3x97. Furthermore, the internal MCLK signal must have an absolute frequency range as dictated by the operating characteristics of the device-internal circuitry.
Typically, the received external MCLK signal is divided by a selected set of divide ratios to generate a set of available internal MCLK signals of corresponding frequencies. Internal circuitry, such as a state machine, then transitions through the available internal MCLK signals until an internal MCLK signal is found which meets the above criteria. This internal MCLK signal is then selected to control the overall timing internal to the device. This process however is subject to significant disadvantages. For example, since a number of possible internal MCLK clock signals are generated, in addition to the actual internal MCLK signal which is required, a substantial amount of unnecessary noise is added to the system. Additionally, the multiplexers normally required to perform the clock selection often introduce transition glitches and xe2x80x9cunsafexe2x80x9d clock signals during the process of testing the available internal MCLK signals to detect the MCLK signal of the proper frequency. (A xe2x80x9csafexe2x80x9d transition between clocks occurs when the logic low period of the selected clock output from the corresponding selection circuitry is not shorter than the shortest logic low period of any of the clocks input to the selection circuitry. Similarly, a safe transition occurs when the logic high period of the selected clock output from the selection circuitry is not shorter than the shortest logic high period of any of the clocks input into the selection circuitry.) Finally, these conventional schemes are difficult to scale and often require the expenditure of significant redesign efforts when a circuit designer attempts to translate a given clock generation design from one chip to another chip.
Hence, new techniques are required for generating internal clock signals, such as the internal MCLK signals used in audio applications. Such techniques should minimize glitches and unsafe clock operating regions during the clock signal generation process, especially during multiplexer switching.
A clock generator circuit includes a counter which counts edges of a received clock signal and a comparator which compares divide ratio control data with a count generated by the counter and generates an active state of a control signal in response. An output flip-flop toggles in response to the control signal and a selected edge of the received clock signal to toggle a state of an output clock signal.
Clock generation circuits and methods embodying the principles of the present invention advantageously reduce system noise since only a single internal clock signal of the derived frequency is generated. Furthermore, according to these principles, the need for an output multiplexer is eliminated, thereby reducing the number of glitches caused during the process of setting the appropriate internal clock frequency. Additionally, embodiments of the present invention allow for the generation of an internal clock with a non-integer frequency ratio with respect to the external clock frequency from which the internal clock is being derived.